It is known for memory devices to have defects which can prevent the device from operating as designed. In particular, defects can occur during the manufacture of memory devices so that memory cells within the array do not operate properly. For example a defect in a memory cell (or associated circuitry) can cause data written to the memory cell to be stored incorrectly or not at all. Furthermore, the defect may prevent the data from being reliably read from the addressed memory cell. Any of these types of defects can reduce the manufacturing yield for the flash memory device.
It is known to include redundant memory cells in the memory, which can selectively replace normal memory cells that are determined to be defective to improve the manufacturing yield of the memory. The addresses associated with the defective memory cells can be stored and compared to addresses associated with memory operations (i.e., read operations and write operations). If the address matches a stored address, a redundancy circuit can re-route (or map) the data to or from the memory so that the defective memory cells are not used for the memory operation. For example, during a write operation, write data (which would otherwise be directed to a known defective memory cell) can be re-routed to a redundant memory cell. Later, when a read operation is directed to the address of the known defective memory cell, the redundant memory cell, as well as the known defective memory cells, is accessed. The data retrieved from the redundant memory cell is re-routed to replace the data that was read from the known defective memory cell to provide the data that was previously written to the accessed address.
The operation of replacing the address corresponding to a failed memory cell with the address of spare cell is sometimes referred to as a fail address programming operation. FIG. 1 is a block diagram showing a conventional fail address programming circuit. The fail address programming circuit 100 is a circuit that stores fail address signals (FAS) generated through the test using internal fuses. The fail address signal stored in the fail address programming circuit 100 is compared to an input write address signal to be used in the elimination of failures from of the memory cell.
Referring to FIG. 1, the conventional fail address programming circuit 100 includes programming cells PCELL1˜PCELLn that program the FAS. The fail address signal FAS is a signal having information about the position of fail cell that is found by the test. The fail address signal FAS is applied to all programming cells PCELL1˜PCELLn.
In addition, the programming cell, to which an activated selection signal is applied, receives and stores the FAS. In addition, the FAS is programmed in response to a programming signal PS. Here, “programming” means that a fuse in the programming cell is connected or blocked by the programming signal PS. It can be assumed that a plurality of fail memory cells are found by the test.
The FAS corresponding to the position of the fail memory cell that is initially found is applied to the programming cells PCELL1˜PCELLn. In addition, a first selection signal S1 is activated. Then, the first programming cell PCELL1 stores the FAS that is found first.
A programming signal PS is applied to the first programming cell PCELL1 through an input pin or a pad 10. Then the first programming cell PCELL1 programs the FAS that is found first.
Then, the FAS corresponding to a position of the fail memory cell that is found second is applied to the programming cells PCELL1˜PCELLn. A second selection signal S2 is activated. Here, the first selection signal S1 is deactivated. Then, the second programming cell PCELL2 stores the fail address signal FAS that is found second.
A programming signal PS is applied to the second programming cell PCELL2 through the input pin or the pad 10. Then, the second programming cell PCELL2 programs the FAS that is found second.
FIG. 2 is a flow chart illustrating a conventional fail address programming method. Referring to FIG. 2, in the conventional fail address programming method 200, when a fail address signal is generated (210), the fail address signal is applied to corresponding programming cell in response to corresponding selection signal (220).
The fail address signal applied to the programming cell is programmed in response to the programming signal (230). If a plurality of fail address signals are generated, that is, a plurality of fail memory cells are found, 210˜230 are repeated until the found fail address signal are all programmed.